I wrote a stereo delay code and it basicly works fine. There is separation between channels.
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.rn in_l r0 ; left input register
.rn in_r r1 ; right input register
.rn out_l r2 ; left output register
.rn out_r r3 ; right output register
.mem delay_l 16383 ; left channel delay block
.mem delay_r 16383 ; right channel delay block
cpy_cs acc32, in0 ; read in left channel into acc
multri acc32, 0.707 ; scale acc by 0.707
cpy_cc in_l, acc32 ; write acc to variable
cpy_cs acc32, in1 ; read in right channel into acc
multri acc32, 0.707 ; scale acc by 0.707
cpy_cc in_r, acc32 ; write acc to variable
wrdel delay_l, in_l ; write left channel to delay head
wrdel delay_r, in_r ; write right channel to delay head
rddel out_l, delay_l# ; read left delay tail into variable
rddel out_r, delay_r# ; read right delay tail into variable
cpy_cc acc32, out_l ; load left delay output into acc
adds acc32, in_l ; add left input
cpy_sc out0, acc32 ; sent it to left dac
cpy_cc acc32, out_r ; load right delay output into acc
adds acc32, in_r ; add right input
cpy_sc out1, acc32 ; sent it to right dac
I tried to add control to interp instruction, like this:
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cpy_cc len, POT0_SMTH
wrdld acc32, 16383
cpy_cc end_r, acc32
multrr acc32, len
cpy_cc end_l, acc32
wrdld acc32, 16383
multrr acc32, len
adds acc32, end_r
cpy_cc end_r, acc32
wrdel 0, temp_l
interp end_l, 32737
cpy_cc temp_l, acc32
wrdel 16384, temp_r
interp end_r, 32737
cpy_cc temp_r, acc32