stacking two FXCore chips
stacking two FXCore chips
Would it be possible to connect the I2s outputs of the FXCore to another FXCore I2s input? So I mean creating a master-slave config. This would give me double the processing power in the digital domain.
Re: stacking two FXCore chips
Yes, in fact they are designed to work that way. Run the second chip in slave mode, pin 21 high for master device and low for slave device. Run the LRCK from the master to the LRCKs on the slave and do the same for the SCKs as well.
Re: stacking two FXCore chips
One more clarifying question.
Is it possible to run the first output I2S into a second fxcore and then out from that one back into the second I2S input of the first fxcore? And then of course, the second I2S output of the first fxcore goes out to the codec. It seems like this should work, but I haven't tried it yet.
Is it possible to run the first output I2S into a second fxcore and then out from that one back into the second I2S input of the first fxcore? And then of course, the second I2S output of the first fxcore goes out to the codec. It seems like this should work, but I haven't tried it yet.
Re: stacking two FXCore chips
Sure, as long as there are enough I2S I/O pins and there is one master so the rest are synced to the same clocks you can do a bunch of different configs depending on product requirements. A few possible examples:
CODEC I2S out - > in 0/1 FXCore 1 / FXCore 1 out 2/3 -> in 0/1 FXCore 2/FXCore 2 out 0/1 -> in 2/3 FXCore 1/FXCore 1 out 0/1 -> CODEC in
or
CODEC I2S out - > in 0/1 FXCore 1 / FXCore 1 out 0/1 -> in 0/1 FXCore 2/FXCore 2 out 0/1 -> CODEC in
In the first chain FXCore 1 does all CODEC I/O, good if you need to mix in the result of what FXCore 2 is doing. In the second chain the CODEC feeds FXCore 1 but gets its data from FXCore 2, good if the programs in each FXCore build on each other and the final result does not need to be sent back to FXCore 1 as this leaves the second channel (in/out 2/3) free on both chips for other uses. This works since all clocks are in sync so all data on the I2S lines should also be in sync, as a result the CODEC doesn't care where the data is coming from.
Both chains can be easily expanded to FXCore 3, 4, 5 ...
CODEC I2S out - > in 0/1 FXCore 1 / FXCore 1 out 2/3 -> in 0/1 FXCore 2/FXCore 2 out 0/1 -> in 2/3 FXCore 1/FXCore 1 out 0/1 -> CODEC in
or
CODEC I2S out - > in 0/1 FXCore 1 / FXCore 1 out 0/1 -> in 0/1 FXCore 2/FXCore 2 out 0/1 -> CODEC in
In the first chain FXCore 1 does all CODEC I/O, good if you need to mix in the result of what FXCore 2 is doing. In the second chain the CODEC feeds FXCore 1 but gets its data from FXCore 2, good if the programs in each FXCore build on each other and the final result does not need to be sent back to FXCore 1 as this leaves the second channel (in/out 2/3) free on both chips for other uses. This works since all clocks are in sync so all data on the I2S lines should also be in sync, as a result the CODEC doesn't care where the data is coming from.
Both chains can be easily expanded to FXCore 3, 4, 5 ...